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» On Bus Graph Realizability
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ICCAD
2003
IEEE
137views Hardware» more  ICCAD 2003»
14 years 3 months ago
Bus-Driven Floorplanning
In this paper, we present an integrated approach to floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus speci...
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
FPL
2007
Springer
146views Hardware» more  FPL 2007»
14 years 13 days ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
ISICT
2003
13 years 7 months ago
An evolutionary approach for reducing the energy in address buses
In this paper we present a genetic approach for the efficient generation of an encoder to minimize switching activity on the high-capacity lines of a communication bus. The appro...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
DM
2008
123views more  DM 2008»
13 years 6 months ago
Graphic sequences with a realization containing a generalized friendship graph
: Gould, Jacobson and Lehel (Combinatorics, Graph Theory and Algorithms, Vol.I (1999) 451
Jian-Hua Yin, Gang Chen, John R. Schmitt
ISQED
2005
IEEE
120views Hardware» more  ISQED 2005»
13 years 12 months ago
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan