3224 search results - page 167 / 645 » On Checking Model Checkers |
125
Voted
QEST
2008
IEEE
15 years 10 months ago
2008
IEEE
CaVi provides a uniform interface to state-of-the-art simulation methods and formal verification methods for wireless sensor network. Simulation is suitable to examine the behavi...
137
Voted
ASPDAC
2007
ACM
15 years 7 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
115
Voted
ACSD
2009
IEEE
15 years 10 months ago
2009
IEEE
We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symb...
193
Voted
CAV
2006
Springer
15 years 7 months ago
2006
Springer
CUTE, a Concolic Unit Testing Engine for C and Java, is a tool to systematically and automatically test sequential C programs (including pointers) and concurrent Java programs. CUT...
115
Voted
FDL
2005
IEEE
15 years 9 months ago
2005
IEEE
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...