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CASES
2010
ACM
14 years 7 months ago
Fine-grain dynamic instruction placement for L0 scratch-pad memory
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
JongSoo Park, James D. Balfour, William J. Dally
86
Voted
IPPS
2010
IEEE
14 years 7 months ago
Dynamic analysis of the relay cache-coherence protocol for distributed transactional memory
Transactional memory is an alternative programming model for managing contention in accessing shared in-memory data objects. Distributed transactional memory (TM) promises to alle...
Bo Zhang, Binoy Ravindran
IGIS
1994
156views GIS» more  IGIS 1994»
15 years 1 months ago
Optimizing Spatial Data Structures For Static Data
During the last decade various spatial data structures have been designed and compared against each other, all of them re ecting a dynamic situation with ongoing object insertion a...
Lukas Bachmann, Bernd-Uwe Pagel, Hans-Werner Six
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
15 years 2 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
114
Voted
EMSOFT
2008
Springer
14 years 10 months ago
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications
Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two popular techniques commonly employed to save energy in real-time embedded systems. DVS policies aim at red...
Vinay Devadas, Hakan Aydin