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DATE
2003
IEEE
128views Hardware» more  DATE 2003»
15 years 11 months ago
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
Given the growth in application-specific processors, there is a strong need for a retargetable modeling framework that is capable of accurately capturing complex processor behavi...
Wei Qin, Sharad Malik
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 11 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
DFT
2003
IEEE
142views VLSI» more  DFT 2003»
15 years 11 months ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato
ECCB
2003
IEEE
15 years 11 months ago
Gene networks inference using dynamic Bayesian networks
This article deals with the identification of gene regulatory networks from experimental data using a statistical machine learning approach. A stochastic model of gene interactio...
Bruno-Edouard Perrin, Liva Ralaivola, Aurél...
FCCM
2003
IEEE
113views VLSI» more  FCCM 2003»
15 years 11 months ago
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
Kenneth Eguro, Scott Hauck
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