7195 search results - page 173 / 1439 » On Computing Power |
117
click to vote
HPCA
2006
IEEE
16 years 1 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
82
Voted
CLUSTER
2007
IEEE
15 years 5 months ago
2007
IEEE
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...
98
Voted
VLSID
2008
IEEE
16 years 1 months ago
2008
IEEE
Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. Howeve...
ISCAS
2006
IEEE
15 years 7 months ago
2006
IEEE
— This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a Power System on a Chip (PSoC). The paper wil...
DAC
1999
ACM
16 years 2 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...