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DSD
2005
IEEE
106views Hardware» more  DSD 2005»
15 years 9 months ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
HOTI
2005
IEEE
15 years 9 months ago
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Pa...
ICCAD
1996
IEEE
131views Hardware» more  ICCAD 1996»
15 years 7 months ago
Multi-level logic optimization for low power using local logic transformations
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
Qi Wang, Sarma B. K. Vrudhula
ISLPED
1996
ACM
102views Hardware» more  ISLPED 1996»
15 years 7 months ago
High-level power estimation and the area complexity of Boolean functions
Estimation of the area complexity of a Boolean function from its functional description is an important step towards a power estimation capability at the register transfer level (...
Mahadevamurty Nemani, Farid N. Najm
SETN
2010
Springer
15 years 7 months ago
Genetic Algorithm Solution to Optimal Sizing Problem of Small Autonomous Hybrid Power Systems
The optimal sizing of a small autonomous hybrid power system can be a very challenging task, due to the large number of design settings and the uncertainty in key parameters. This ...
Yiannis A. Katsigiannis, Pavlos S. Georgilakis, Em...