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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 1 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
BIRTHDAY
2009
Springer
15 years 11 months ago
Is the World Linear?
Super-resolution is the art of creating nice high-resolution raster images from given low-resolution raster images. Since “nice” is not a well-defined term in mathematics and ...
Rudolf Fleischer
157
Voted
IPPS
2009
IEEE
15 years 10 months ago
An upload bandwidth threshold for peer-to-peer Video-on-Demand scalability
We consider the fully distributed Video-on-Demand problem, where n nodes called boxes store a large set of videos and collaborate to serve simultaneously n videos or less between ...
Yacine Boufkhad, Fabien Mathieu, Fabien de Montgol...
INFOCOM
2008
IEEE
15 years 10 months ago
Queueing Analysis of Loss Systems with Variable Optical Delay Lines
—Recently, a new optical device called variable optical delay line (VODL) has been proposed in the literature. As suggested by its name, the delay of a VODL can be dynamically se...
Duan-Shin Lee, Cheng-Shang Chang, Jay Cheng, Horng...
INFOCOM
2007
IEEE
15 years 10 months ago
Feedforward SDL Constructions of Output-Buffered Multiplexers and Switches with Variable Length Bursts
Abstract— In this paper, we study the problem of exact emulation of two types of optical queues: (i) N-to-1 output-buffered multiplexers with variable length bursts, and (ii) N ...
Yi-Ting Chen, Cheng-Shang Chang, Jay Cheng, Duan-S...