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FPGA
1998
ACM
125views FPGA» more  FPGA 1998»
15 years 1 months ago
Timing Driven Floorplanning on Programmable Hierarchical Targets
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
S. A. Senouci, A. Amoura, Helena Krupnova, Gabriel...
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
15 years 1 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
DAC
2005
ACM
14 years 11 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
ENTCS
2008
115views more  ENTCS 2008»
14 years 9 months ago
Time Separation of Events: An Inverse Method
The problem of "time separation" can be stated as follows: Given a system made of several connected components, each one entailing a local delay known with uncertainty, ...
Emmanuelle Encrenaz, Laurent Fribourg
IPPS
2003
IEEE
15 years 2 months ago
Task Graph Scheduling Using Timed Automata
In this paper we develop a methodology for treating the problem of scheduling partially-ordered tasks on parallel machines. Our framework is based on the timed automaton model, or...
Yasmina Abdeddaïm, Abdelkarim Kerbaa, Oded Ma...