87 search results - page 8 / 18 » On Discretization of Delays in Timed Automata and Digital Ci... |
CDC
2008
IEEE
15 years 4 months ago
2008
IEEE
— We propose a diagnosability notion that depends on two parameters denoted as (δd, δm) for the general class of transition systems where the observable output is given by disc...
82
Voted
ISPD
2003
ACM
15 years 2 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
COORDINATION
2009
Springer
15 years 25 days ago
2009
Springer
Abstract. Reo is a channel-based coordination model whose operational semantics is given by Constraint Automata (CA). Quantitative Constraint Automata extend CA (and hence, Reo) wi...
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
65
Voted
ICCAD
1998
IEEE
15 years 1 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...