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» On Doubly-Cyclic Convolutional Codes
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ISLPED
2003
ACM
111views Hardware» more  ISLPED 2003»
15 years 2 months ago
A low-power VLSI architecture for turbo decoding
Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block...
Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
IJACTAICIT
2010
136views more  IJACTAICIT 2010»
14 years 7 months ago
Performance Enhancement of Wireless Communication Systems using Transmit and Receive diversity
In this paper, we describe the concatenation of Turbo/Convolutional codes with transmit and receive diversity schemes by using Space-Time Block Code. It is shown that, by using tw...
Ahmed J. Jameel
SIPS
2008
IEEE
15 years 4 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
67
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ISCAS
2007
IEEE
117views Hardware» more  ISCAS 2007»
15 years 4 months ago
Quantifying Input and Output Spike Statistics of a Winner-Take-All Network in a Vision System
— Event-driven spike-based processing systems offer new possibilities for real-time vision. Signals are encoded asynchronously in time thus preserving the time information of the...
Matthias Oster, Rodney J. Douglas, Shih-Chii Liu
VTC
2008
IEEE
15 years 4 months ago
Irregular Precoder-Aided Differential Linear Dispersion Codes
—In this treatise, we propose a novel family of serial concatenated IrRegular Convolutional Coded (IRCC) IrRegular Precoded Differential Linear Dispersion Codes (IR-PDLDC). The i...
Nan Wu, Lajos Hanzo