ABSTRACT. Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and r...
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
Prasad A. Kulkarni, Michael R. Jantz, David B. Wha...
We investigate the trade off between investing effort in improving the features of a research environment that increases productivity and investing such effort in actually conduct...
Juan C. Quiroz, Anil Shankar, Sergiu M. Dascalu, S...
We propose a two-state Markov chain model of degraded document images. The model generates random and burst noise to simulate isolated pixel reversal as well as blurring of a larg...