216 search results - page 17 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
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HPCA
2009
IEEE
16 years 6 days ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
86
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ICPADS
1994
IEEE
15 years 3 months ago
1994
IEEE
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
107
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SIGCSE
1999
ACM
15 years 4 months ago
1999
ACM
The wide-spread use of microprocessor based systems that utilize cache memory to alleviate excessively long DRAM access times introduces a new dimension in the quest to obtain goo...
HPCA
1997
IEEE
15 years 3 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
MICRO
2008
IEEE
15 years 6 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...