216 search results - page 26 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
137
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ISCA
1994
IEEE
15 years 9 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
159
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HOTI
2005
IEEE
15 years 10 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
154
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ISCA
2005
IEEE
15 years 10 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
140
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ASPLOS
2008
ACM
15 years 7 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
163
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IPCCC
2006
IEEE
15 years 11 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...