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DAC
2009
ACM
15 years 11 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
SEMWEB
2004
Springer
15 years 3 months ago
Query Answering for OWL-DL with Rules
Both OWL-DL and function-free Horn rules3 are decidable logics with interesting, yet orthogonal expressive power: from the rules perspective, OWL-DL is restricted to tree-like rule...
Boris Motik, Ulrike Sattler, Rudi Studer
SIGSOFT
2003
ACM
15 years 3 months ago
Fluent model checking for event-based systems
Model checking is an automated technique for verifying that a system satisfies a set of required properties. Such properties are typically expressed as temporal logic formulas, in...
Dimitra Giannakopoulou, Jeff Magee
FROCOS
2007
Springer
15 years 1 months ago
From KSAT to Delayed Theory Combination: Exploiting DPLL Outside the SAT Domain
In the last two decades we have witnessed an impressive advance in the efficiency of propositional satisfiability techniques (SAT), which has brought large and previously-intractab...
Roberto Sebastiani
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
15 years 1 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl