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» On Hybrid Combination of Queueing and Simulation
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ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
15 years 4 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
15 years 5 months ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
BMCBI
2011
14 years 6 months ago
DecGPU: distributed error correction on massively parallel graphics processing units using CUDA and MPI
Background: Next-generation sequencing technologies have led to the high-throughput production of sequence data (reads) at low cost. However, these reads are significantly shorter...
Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
BMCBI
2010
108views more  BMCBI 2010»
14 years 11 months ago
A genetic ensemble approach for gene-gene interaction identification
Background: It has now become clear that gene-gene interactions and gene-environment interactions are ubiquitous and fundamental mechanisms for the development of complex diseases...
Pengyi Yang, Joshua W. K. Ho, Albert Y. Zomaya, Bi...
ICC
2007
IEEE
138views Communications» more  ICC 2007»
15 years 6 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi