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ICCAD
1997
IEEE
91views Hardware» more  ICCAD 1997»
15 years 4 months ago
Interconnect layout optimization under higher-order RLC model
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
Jason Cong, Cheng-Kok Koh
ICLP
1997
Springer
15 years 4 months ago
The Complexity of Model Checking in Modal Event Calculi
Kowalski and Sergot’s Event Calculus (EC) is a simple temporal formalism that, given a set of event occurrences, derives the maximal validity intervals (MVIs) over which propert...
Iliano Cervesato, Massimo Franceschet, Angelo Mont...
SIGGRAPH
1994
ACM
15 years 3 months ago
FBRAM: a new form of memory optimized for 3D graphics
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
Michael F. Deering, Stephen A. Schlapp, Michael G....
CSR
2006
Springer
15 years 3 months ago
Window Subsequence Problems for Compressed Texts
Given two strings (a text t of length n and a pattern p) and a natural number w, window subsequence problems consist in deciding whether p occurs as a subsequence of t and/or findi...
Patrick Cégielski, Irène Guessarian,...
CAV
2001
Springer
80views Hardware» more  CAV 2001»
15 years 3 months ago
Transformation-Based Verification Using Generalized Retiming
In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based...
Andreas Kuehlmann, Jason Baumgartner