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2003
IEEE
97views Hardware» more  DATE 2003»
15 years 11 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
IPPS
2003
IEEE
15 years 11 months ago
Performing DNA Comparison on a Bio-Inspired Tissue of FPGAs
String comparison is a critical issue in many application domains, including speech recognition, contents search, and bioinformatics. The similarity between two strings of lengths...
Matteo Canella, Filippo Miglioli, Alessandro Bogli...
KBSE
2003
IEEE
15 years 11 months ago
A Programmable Client-Server Model: Robust Extensibility via DSLs
The client-server model has been successfully used to support a wide variety of families of services in the context of distributed systems. However, its server-centric nature make...
Charles Consel, Laurent Réveillère
PPOPP
2003
ACM
15 years 11 months ago
Exploiting high-level coherence information to optimize distributed shared state
InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating ...
DeQing Chen, Chunqiang Tang, Brandon Sanders, Sand...
CP
2003
Springer
15 years 11 months ago
Generating High Quality Schedules for a Spacecraft Memory Downlink Problem
This work introduces a combinatorial optimization problem called Mars Express Memory Dumping Problem (Mex-Mdp), which arises in the European Space Agency program Mars Express. It c...
Angelo Oddi, Nicola Policella, Amedeo Cesta, Gabri...