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ACSAC
2000
IEEE
15 years 8 months ago
Layering Boundary Protections: An Experiment in Information Assurance
The DARPA Information Assurance Program has the aim of developing and executing experiments that test specific hypotheses about defense in depth and dynamic defense capabilities. ...
D. Johnson, L. Benzinger
APCSAC
2000
IEEE
15 years 8 months ago
Micro-Threading: A New Approach to Future RISC
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
Chris R. Jesshope, Bing Luo
IEEEPACT
2000
IEEE
15 years 8 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
IPPS
2000
IEEE
15 years 8 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 8 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi