Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
Since sensor data gathering is the primary functionality of sensor networks, it is important to provide a fault tolerant method for reasoning about sensed events in the face of ar...
Mark D. Krasniewski, Padma Varadharajan, Bryan Rab...
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
This article formalises the dual problem to model-based diagnosis (MBD), i.e., generating tests to isolate multiple simultaneous faults. Using a standard propositional MBD framewo...
This paper proposes a novel subspace approach towards direct identification of a residual model for fault detection and isolation (FDI) in a system with non-uniformly sampled mult...