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» On Parallel Execution of Multiple Pipelined Hash Joins
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CSE
2011
IEEE
13 years 11 months ago
Performance Enhancement of Network Devices with Multi-Core Processors
— In network based applications, packet capture is the main area that attracts many researchers in developing traffic monitoring systems. Along with the packet capture, many othe...
Nhat-Phuong Tran, Sugwon Hong, Myungho Lee, Seung-...
ACSAC
2000
IEEE
15 years 4 months ago
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
Johann Großschädl
ISHPC
2003
Springer
15 years 5 months ago
Tolerating Branch Predictor Latency on SMT
Abstract. Simultaneous Multithreading (SMT) tolerates latency by executing instructions from multiple threads. If a thread is stalled, resources can be used by other threads. Howev...
Ayose Falcón, Oliverio J. Santana, Alex Ram...
COOPIS
2004
IEEE
15 years 3 months ago
A Distributed and Parallel Component Architecture for Stream-Oriented Applications
Abstract. This paper introduces ThreadMill - a distributed and parallel component architecture for applications that process large volumes of streamed (time-sequenced) data, such a...
Paulo Barthelmess, Clarence A. Ellis
165
Voted
SIGMOD
2007
ACM
136views Database» more  SIGMOD 2007»
15 years 12 months ago
Progressive optimization in a shared-nothing parallel database
Commercial enterprise data warehouses are typically implemented on parallel databases due to the inherent scalability and performance limitation of a serial architecture. Queries ...
Wook-Shin Han, Jack Ng, Volker Markl, Holger Kache...