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» On Proving the Absence of Oscillations in Models of Genetic ...
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AB
2007
Springer
15 years 4 months ago
On Proving the Absence of Oscillations in Models of Genetic Circuits
François Boulier, Marc Lefranc, Franç...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...
CN
2006
70views more  CN 2006»
14 years 10 months ago
Preventing persistent oscillations and loops in IBGP configuration with route reflection
Abstract-- Internal Border Gateway Protocol (IBGP) is responsible for distributing external reachability information, obtained via External-BGP (EBGP) sessions, within an autonomou...
Anuj Rawat, Mark A. Shayman
ICCD
2001
IEEE
88views Hardware» more  ICCD 2001»
15 years 6 months ago
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
Payam Heydari, Massoud Pedram