8728 search results - page 129 / 1746 » On Reduct Construction Algorithms |
94
Voted
PCM
2004
Springer
15 years 6 months ago
2004
Springer
In previous techniques of bit rate reduction transcoding, reusing the mode of the input MB is widely adopted. However, directly re-using the mode of input MB will cause additional ...
91
Voted
DAC
1999
ACM
15 years 5 months ago
1999
ACM
ENOR is an innovative way to produce provablypassive, reciprocal, and compact representations of RLC circuits. Beginning with the nodal equations, ENOR formulates recurrence relat...
FTML
2010
14 years 11 months ago
2010
We give a tutorial overview of several geometric methods for dimension reduction. We divide the methods into projective methods and methods that model the manifold on which the da...
87
Voted
GLVLSI
2005
IEEE
15 years 6 months ago
2005
IEEE
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
ICCAD
2006
IEEE
15 years 9 months ago
2006
IEEE
— In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, ea...