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» On Reduction of Lagrange Systems
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EURODAC
1995
IEEE
131views VHDL» more  EURODAC 1995»
15 years 9 months ago
System level design, a VHDL based approach
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Market reductions. The system design flow provides for codesign of (embedded) driv...
Joris van den Hurk, Edwin Dilling
LISA
2007
15 years 8 months ago
ATLANTIDES: An Architecture for Alert Verification in Network Intrusion Detection Systems
We present an architecture1 designed for alert verification (i.e., to reduce false positives) in network intrusion-detection systems. Our technique is based on a systematic (and a...
Damiano Bolzoni, Bruno Crispo, Sandro Etalle
MR
2007
120views Robotics» more  MR 2007»
15 years 5 months ago
Advanced electronic prognostics through system telemetry and pattern recognition methods
Electronic Prognostics (EP) is a technique used in high-reliability and high-availability systems to actively and proactively detect faults, allowing the reduction of system downt...
Leon Lopez
ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
16 years 2 months ago
Performance analysis of concurrent systems with early evaluation
Early evaluation allows to execute operations when enough information at the inputs has been received to determine the value at the outputs. Systems that can tolerate variable-lat...
Jorge Júlvez, Jordi Cortadella, Michael Kis...
ESSOS
2009
Springer
16 years 23 days ago
MEDS: The Memory Error Detection System
Abstract. Memory errors continue to be a major source of software failure. To address this issue, we present MEDS (Memory Error Detection System), a system for detecting memory err...
Jason Hiser, Clark L. Coleman, Michele Co, Jack W....