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» On Reduction of Lagrange Systems
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ICIP
2003
IEEE
16 years 7 months ago
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores
For motion estimation (ME) and discrete cosine transform (DCT) of MPEG video encoding, content variation and perceptual tolerance in video signals can be exploited to gracefully t...
Andrew Laffely, Jian Liang, Russell Tessier, Wayne...
DAC
2008
ACM
16 years 7 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
DAC
2002
ACM
16 years 7 months ago
Exploiting shared scratch pad memory space in embedded multiprocessor systems
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...
Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhar...
EDBT
2006
ACM
112views Database» more  EDBT 2006»
16 years 6 months ago
Indexing Shared Content in Information Retrieval Systems
Abstract. Modern document collections often contain groups of documents with overlapping or shared content. However, most information retrieval systems process each document separa...
Andrei Z. Broder, Nadav Eiron, Marcus Fontoura, Mi...
ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
16 years 3 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang