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» On Reduction of Lagrange Systems
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ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
15 years 4 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 4 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
ICDCS
2008
IEEE
15 years 4 months ago
Correlation-Aware Object Placement for Multi-Object Operations
A multi-object operation incurs communication or synchronization overhead when the requested objects are distributed over different nodes. The object pair correlations (the probab...
Ming Zhong, Kai Shen, Joel I. Seiferas
FOCS
2007
IEEE
15 years 4 months ago
Adaptive Simulated Annealing: A Near-optimal Connection between Sampling and Counting
We present a near-optimal reduction from approximately counting the cardinality of a discrete set to approximately sampling elements of the set. An important application of our wo...
Daniel Stefankovic, Santosh Vempala, Eric Vigoda
LCTRTS
2007
Springer
15 years 4 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier