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» On Reduction of Lagrange Systems
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ISCA
2005
IEEE
121views Hardware» more  ISCA 2005»
15 years 3 months ago
Direct Cache Access for High Bandwidth Network I/O
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Ram Huggahalli, Ravi R. Iyer, Scott Tetrick
ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
15 years 3 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
15 years 3 months ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng
PADS
2005
ACM
15 years 3 months ago
Concurrent Replication of Parallel and Distributed Simulations
Parallel and distributed simulations enable the analysis of complex systems by concurrently exploiting the aggregate computation power and memory of clusters of execution units. I...
Luciano Bononi, Michele Bracuto, Gabriele D'Angelo...
SIGSOFT
2005
ACM
15 years 3 months ago
Reuse and variability in large software applications
Reuse has always been a major goal in software engineering, since it promises large gains in productivity, quality and time to market reduction. Practical experience has shown tha...
Jacky Estublier, Germán Vega