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» On Reduction of Lagrange Systems
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GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan
HICSS
2003
IEEE
138views Biometrics» more  HICSS 2003»
15 years 3 months ago
Towards Verifying Parametrised Hardware Libraries with Relative Placement Information
Abstract— This paper presents a framework for verifying compilation tools for parametrised hardware libraries with placement information. Such libraries are captured in Pebble, a...
Steve McKeever, Wayne Luk, Arran Derbyshire
IPPS
2003
IEEE
15 years 3 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
IMC
2003
ACM
15 years 3 months ago
Virtual landmarks for the internet
Internet coordinate schemes have been proposed as a method for estimating minimum round trip time between hosts without direct measurement. In such a scheme, each host is assigned...
Liying Tang, Mark Crovella
SC
2003
ACM
15 years 3 months ago
Scalable Hardware-Based Multicast Trees
This paper presents an algorithm for implementing optimal hardware-based multicast trees, on networks that provide hardware support for collective communication. Although the prop...
Salvador Coll, José Duato, Fabrizio Petrini...