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» On Reduction of Lagrange Systems
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234
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SIGMOD
2002
ACM
246views Database» more  SIGMOD 2002»
16 years 6 months ago
Hierarchical subspace sampling: a unified framework for high dimensional data reduction, selectivity estimation and nearest neig
With the increased abilities for automated data collection made possible by modern technology, the typical sizes of data collections have continued to grow in recent years. In suc...
Charu C. Aggarwal
CODES
2007
IEEE
16 years 5 days ago
Smart driver for power reduction in next generation bistable electrophoretic display technology
Microencapsulated electrophoretic displays (EPDs) are quickly emerging as an important technology for use in battery-powered portable computing devices. Thanks to bistability and ...
Michael A. Baker, Aviral Shrivastava, Karam S. Cha...
MSS
2005
IEEE
62views Hardware» more  MSS 2005»
15 years 11 months ago
Predictive Reduction of Power and Latency (PuRPLe)
Increasing efforts have been aimed towards the management of power as a critical system resource, and the disk can consume approximately a third of the power required for a typica...
Matthew Craven, Ahmed Amer
190
Voted
AGTIVE
2003
Springer
15 years 11 months ago
Specifying Pointer Structures by Graph Reduction
Graph-reduction specifications (GRSs) are a powerful new method for specifying classes of pointer data structures (shapes). They cover important shapes, like various forms of bal...
Adam Bakewell, Detlef Plump, Colin Runciman
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
16 years 4 days ago
Reduction of detected acceptable faults for yield improvement via error-tolerance
Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was pro...
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer