123 search results - page 10 / 25 » On Statistical Timing Analysis with Inter- and Intra-Die Var... |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for...
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ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. In the past few years, while much research has...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...