123 search results - page 14 / 25 » On Statistical Timing Analysis with Inter- and Intra-Die Var... |
DAC
1999
ACM
15 years 2 months ago
1999
ACM
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
FPGA
2007
ACM
15 years 3 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitiviti...