123 search results - page 7 / 25 » On Statistical Timing Analysis with Inter- and Intra-Die Var... |
ISQED
2007
IEEE
15 years 4 months ago
2007
IEEE
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
IDEAL
2004
Springer
15 years 3 months ago
2004
Springer
Many time series exhibit dynamics over vastly different time scales. The standard way to capture this behavior is to assume that the slow dynamics are a “trend”, to de-trend t...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...