123 search results - page 9 / 25 » On Statistical Timing Analysis with Inter- and Intra-Die Var... |
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TCAD
2008
14 years 9 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...