82 search results - page 4 / 17 » On Structural vs. Functional Testing for Delay Faults |
DATE
2007
IEEE
14 years 18 days ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
ATS
1998
IEEE
13 years 10 months ago
1998
IEEE
ESERNET
2003
Springer
13 years 11 months ago
2003
Springer
The origin of the study described here is the experiment performed by Basili and Selby, further replicated by Kamsties and Lott, and once again by Wood et al. These experiments inv...
ITC
1993
IEEE
13 years 10 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
ATS
2003
IEEE
13 years 11 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...