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» On Test Scheduling for Core-Based SOCs
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VTS
2003
IEEE
83views Hardware» more  VTS 2003»
15 years 2 months ago
SOC Test Scheduling Using Simulated Annealing
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Hua...
ATS
2004
IEEE
69views Hardware» more  ATS 2004»
15 years 1 months ago
Pair Balance-Based Test Scheduling for SOCs
Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
ISVLSI
2008
IEEE
152views VLSI» more  ISVLSI 2008»
15 years 3 months ago
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
Julien Dalmasso, Érika F. Cota, Marie-Lise ...
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 2 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...