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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 1 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
SBBD
2004
137views Database» more  SBBD 2004»
14 years 11 months ago
A Lock Manager for Collaborative Processing of Natively Stored XML Documents
Today, neither transactional provisions, in general, nor concurrency control, in particular, of DBMS-based processing are tailored to the specific needs of large and collaborative...
Michael Peter Haustein, Theo Härder
APLAS
2007
ACM
15 years 1 months ago
Scalable Simulation of Cellular Signaling Networks
Abstract. Given the combinatorial nature of cellular signalling pathways, where biological agents can bind and modify each other in a large number of ways, concurrent or agent-base...
Vincent Danos, Jérôme Feret, Walter F...
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
15 years 2 months ago
Digital statistical analysis using VHDL
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
Manfred Dietrich, Uwe Eichler, Joachim Haase
ICMCS
1999
IEEE
94views Multimedia» more  ICMCS 1999»
15 years 2 months ago
Multi-Phase Interval Caching for a News on Demand Server
In this paper, we propose a buffer cache algorithm to build a cost effective storage server for real time news objects. In a News On Demand Server, the number of concurrent stream...
Yong Woon Park, Won Il Seo, Ki-Dong Chung