Sciweavers

1529 search results - page 11 / 306
» On Timing Analysis of Combinational Circuits
Sort
View
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
15 years 1 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 1 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
ICNS
2009
IEEE
14 years 7 months ago
Cost-Effective Burst-Over-Circuit-Switching in a Hybrid Optical Network
All optical switching has been proposed as a candidate to allow high capacity networking in the future. Currently, Optical Circuit Switching has been widely deployed, although thi...
Jens Buysse, Marc De Leenheer, Chris Develder, Bar...
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
15 years 2 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
DAC
2006
ACM
15 years 10 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu