1529 search results - page 12 / 306 » On Timing Analysis of Combinational Circuits |
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
Abstract— Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored...
ICCAD
1993
IEEE
15 years 1 months ago
1993
IEEE
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
UAI
1996
14 years 11 months ago
1996
In this paper we propose a family of algorithms combining treeclustering with conditioning that trade space for time. Such algorithms are useful for reasoning in probabilistic and...
ISPD
2000
ACM
15 years 2 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...