1529 search results - page 13 / 306 » On Timing Analysis of Combinational Circuits |
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
While fast timing analysis methods, such as asymptotic waveform evaluation (AWE), have been well established for linear circuits, the timing analysis for non-linear circuits, whic...
74
Voted
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...