1529 search results - page 14 / 306 » On Timing Analysis of Combinational Circuits |
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Existing static timing analyzers make several assumptions about circuits, implicitly trading off accuracy for speed. In this paper we examine the validity of these assumptions, no...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
ASYNC
2007
IEEE
15 years 4 months ago
2007
IEEE
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...