1529 search results - page 16 / 306 » On Timing Analysis of Combinational Circuits |
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
VLSID
2006
IEEE
15 years 10 months ago
2006
IEEE
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
ICCAD
2000
IEEE
15 years 2 months ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
CHINAF
2006
14 years 9 months ago
2006
: With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical d...
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
In this paper, an analysis of test time by CBET (which is an acronym for Combination of BIST and External Test) test approach is presented. The analysis validates that CBET test a...