1529 search results - page 17 / 306 » On Timing Analysis of Combinational Circuits |
FM
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. We present a new domain for analyzing must-equalities between address expressions. The domain is a smooth combination of Herbrand and affine equalities which enables us t...
115
click to vote
FM
2003
Springer
15 years 2 months ago
2003
Springer
We present a semantics for fault tree analysis, a technique used for the analysis of safety critical systems, in the real-time interval logic Duration Calculus with Liveness and sh...
84
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
We propose a scalable and efficient parameterized block-based statistical static timing analysis algorithm incorporating both Gaussian and non-Gaussian parameter distributions, ca...
88
Voted
DFT
2003
IEEE
15 years 2 months ago
2003
IEEE
Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...
DELTA
2006
IEEE
15 years 1 months ago
2006
IEEE
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...