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» On Timing Analysis of Combinational Circuits
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78
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CG
2005
Springer
14 years 9 months ago
Combining geometry and domain knowledge to interpret hand-drawn diagrams
One main challenge in building interpreters for hand-drawn sketches is the task of parsing a sketch to locate the individual symbols. Many existing pen-based systems avoid this pr...
Leslie Gennari, Levent Burak Kara, Thomas F. Staho...
ICCAD
1999
IEEE
72views Hardware» more  ICCAD 1999»
15 years 1 months ago
An integrated algorithm for combined placement and libraryless technology mapping
This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless ma...
Yanbin Jiang, Sachin S. Sapatnekar
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
15 years 1 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
15 years 1 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
76
Voted
ASPDAC
2007
ACM
105views Hardware» more  ASPDAC 2007»
15 years 1 months ago
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming
Abstract-- In this paper we present the Statistical Retimingbased Timing Analysis (SRTA) algorithm. The goal is to compute the timing slack distribution for the nodes in the timing...
Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim