Sciweavers

1529 search results - page 24 / 306
» On Timing Analysis of Combinational Circuits
Sort
View
73
Voted
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Statistical timing verification for transparently latched circuits through structural graph traversal
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang
CODES
2005
IEEE
15 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICCAD
1994
IEEE
95views Hardware» more  ICCAD 1994»
15 years 1 months ago
Provably correct high-level timing analysis without path sensitization
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
TCAD
2010
164views more  TCAD 2010»
14 years 4 months ago
Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. How...
Javid Jaffari, Mohab Anis
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
15 years 3 months ago
A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems
—Presented are a methodology and a DFII-based tool for AC-stability analysis of a wide variety of closed-loop continuous-time (operational amplifiers and other linear circuits). ...
Momchil Milev, Rod Burt