1529 search results - page 25 / 306 » On Timing Analysis of Combinational Circuits |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
61
Voted
ITC
1996
IEEE
15 years 1 months ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
69
Voted
ASYNC
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...