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» On Timing Analysis of Combinational Circuits
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DATE
2004
IEEE
142views Hardware» more  DATE 2004»
15 years 1 months ago
Eliminating False Positives in Crosstalk Noise Analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Mal...
ICCAD
2009
IEEE
126views Hardware» more  ICCAD 2009»
14 years 7 months ago
Timing Arc based logic analysis for false noise reduction
The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it ...
Murthy Palla, Jens Bargfrede, Stephan Eggersgl&uum...
ISQED
2009
IEEE
103views Hardware» more  ISQED 2009»
15 years 4 months ago
A systematic approach to modeling and analysis of transient faults in logic circuits
With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of th...
Natasa Miskov-Zivanov, Diana Marculescu
CCECE
2011
IEEE
13 years 9 months ago
Mode-matching analysis of substrate-integrated waveguide circuits
A mode-matching approach is presented for the analysis of substrate-integrated waveguide (SIW) circuits. The numerical technique takes advantage of recently developed fabrication ...
Jens Bornemann, Farzaneh Taringou
DAC
2005
ACM
14 years 11 months ago
Piece-wise approximations of RLCK circuit responses using moment matching
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu