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» On Timing Analysis of Combinational Circuits
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ICCAD
2001
IEEE
104views Hardware» more  ICCAD 2001»
15 years 6 months ago
A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
Clayton B. McDonald, Randal E. Bryant
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
15 years 3 months ago
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chun...
CHES
2010
Springer
187views Cryptology» more  CHES 2010»
14 years 10 months ago
Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs - (Full Version)
The power of side-channel leakage attacks on cryptographic implementations is evident. Today's practical defenses are typically attack-specific countermeasures against certain...
Kimmo Järvinen, Vladimir Kolesnikov, Ahmad-Re...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 3 months ago
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits
In this paper we present a method which allows the statistical analysis of nanoelectronic Boolean networks with respect to timing uncertainty and noise. All signals are considered...
Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred G...
ICC
2007
IEEE
106views Communications» more  ICC 2007»
15 years 4 months ago
Hybrid-ARQ Code Combining for MIMO Using Multidimensional Space-Time Trellis Codes
— A hybrid automatic repeat-request (ARQ) code combining scheme employing different multidimensional spacetime trellis codes (MSTTCs) over a multiple-input, multipleoutput (MIMO)...
Zhihong Ding, Michael Rice