1529 search results - page 31 / 306 » On Timing Analysis of Combinational Circuits |
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
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TWC
2008
14 years 9 months ago
2008
We combine space-time coding and transmit beamforming over multiple-antenna quasi-static fading channels using resolution-constrained channel state information at the transmitter ...
AICCSA
2006
IEEE
14 years 11 months ago
2006
IEEE
To excite a stuck-open fault in a CMOS combinational circuit, it is only necessary that the output of the gate containing the fault takes on opposite values during the application...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...