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» On Timing Analysis of Combinational Circuits
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76
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DAC
2005
ACM
14 years 11 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
90
Voted
DAC
2004
ACM
15 years 10 months ago
STAC: statistical timing analysis with correlation
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
Jiayong Le, Xin Li, Lawrence T. Pileggi
DATE
2007
IEEE
130views Hardware» more  DATE 2007»
15 years 4 months ago
A novel criticality computation method in statistical timing analysis
Abstract— The impact of process variations increases as technology scales to nanometer region. Under large process variations, the path and arc/node criticality [18] provide effe...
Feng Wang 0004, Yuan Xie, Hai Ju
ICCD
2000
IEEE
123views Hardware» more  ICCD 2000»
15 years 6 months ago
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...
Payam Heydari, Massoud Pedram
CVPR
2003
IEEE
15 years 11 months ago
Visual Hull Alignment and Refinement Across Time: A 3D Reconstruction Algorithm Combining Shape-From-Silhouette with Stereo
Visual Hull (VH) construction from silhouette images is a popular method of shape estimation. The method, also known as Shape-From-Silhouette (SFS), is used in many applications s...
German K. M. Cheung, Simon Baker, Takeo Kanade