1529 search results - page 38 / 306 » On Timing Analysis of Combinational Circuits |
NAACL
2007
14 years 11 months ago
2007
In the framework of the Tc-Star project, we analyze and propose a combination of two Statistical Machine Translation systems: a phrase-based and an N-gram-based one. The exhaustiv...
HASE
1998
IEEE
15 years 1 months ago
1998
IEEE
Fault trees provide a graphical and logical framework for analyzing the reliability of systems. A fault tree provides a conceptually simple modeling framework to represent the sys...
82
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
89
Voted
ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...