1529 search results - page 44 / 306 » On Timing Analysis of Combinational Circuits |
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
ET
2000
14 years 9 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
DOCENG
2007
ACM
15 years 1 months ago
2007
ACM
We present in this paper a method for document layout analysis based on identifying the function of document elements (what they do). This approach is orthogonal and complementary...
107
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GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...